Conventional processor architectures include table-based control circuits for implementing processor "macro" instructions in microcode. Specifically, the microcode execution datapath is specified by a finite-state table-based control unit, implemented, for example, in a read only memory ("ROM") or Programmable Logic Array ("PLA"). The control unit, in response to a control input (e.g., a macroinstruction opcode), provides a state designation that tells the datapath what needs to be done to execute the "macro" instruction to which the control input corresponds.
Similarly, processor macroinstructions are typically stored in a ROM. A macroinstruction is provided from a data output of the ROM by strobing a read input concurrently with the ROM address of the macroinstruction being provided on an address bus.
With the quest for greater processor miniaturization, it is becoming necessary to further decrease the amount of power that processors consume. Thus, there is a need for table-based control circuits that can be optimized for lower-power consumption.